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1 ?2017 integrated device technology, inc. july 17, 2017 de sc ript ion the 8SLVS1118 is a high-performance, low-power, differential 1:18 output fanout buffer. this highly versatile device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. guaranteed output-to-output and part-to-part skew characteristics make the 8SLVS1118 ideal for clock distribution applications that demand well-defined performance and repeatability. the device is characterized to operate from a 2.5v or 3.3v power supply. the integrated bias voltage references enable easy interfacing ac-coupled signals to the device inputs. fe a t ure s ? 1:18, low skew, low additive jitter lvpecl/lvds fanout buffer ? low power consumption ? differential pclk, npclk clock pair accepts the following differential/single-ended input levels: lvds, lvpecl, and lvcmos ? maximum input clock frequency: 2ghz ? propagation delay: 290ps (typical) ? output skew: 40ps (typical) ? low additive phase jitter, rms: 39fs (typical), integration range: 12khz C 20mhz, (f ref ? 156.25mhz, v pp ? 1v, v dd ? 3.3v) ? full 2.5v and 3.3v supply voltage modes ? device current consumption: 180ma (typical) iee for lvpecl output mode, 400ma (typical) idd for lvds output mode ? 48-vfqfn, lead-free (rohs 6) packaging ? transistor count: 1762 ? -40c to +85c ambient operating temperature ? supports case temperature up to 105c bloc k dia gra m pclk npclk 51k vref sel_lvds pull-down pull-down pull-up / pull-down 51k 51k 51k q0nq0 q1 nq1 q2 nq2 q17 nq17 .. . voltage reference 8slv1118i 8 slv s1 1 1 8 da t a she e t 1 :1 8 , low sk e w , low addit ive j it t e r lv ds/ lv pecl fa nout buffe r
2 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet pin assignm e nt figure 1 . pin assignm e nt for 7 m m ? 7 m m v fqfn pa c k a ge C t op v ie w pin de sc ript ions t a ble 1 . pin de sc ript ions [a ] number name type description 1 gnd power ground supply pin. 2 q16 output differential output pair. lvpecl/ lvds interface levels. 3 nq16 output differential output pair. lvpecl/ lvds interface levels. 4 q17 output differential output pair. lvpecl/ lvds interface levels. 5 nq17 output differential output pair. lvpecl/ lvds interface levels. 6v dd power output power supply pin. 7v dd_in power power supply pin. 8 vref output bias voltage reference for the pclk, npclk input pair. 9 npclk input [pd/pu] inverting differential clock/data input. 10 pclk input [pd] non-inverting differential clock/data input. 11 sel_lvds input [pd] control input. output amplitude select for differential outputs. 12 gnd power power supply ground. 13 v dd power output power supply pin. 14 q0 output differential output pair. lvpecl/ lvds interface levels. 15 nq0 output differential output pair. lvpecl/ lvds interface levels. 16 q1 output differential output pair. lvpecl/ lvds interface levels. nq14 nq13 q13 nq12 q12 nq11 q11 v dd nq15 q15 q14 v dd q1 q2 nq2 q3 nq3 q4 nq4 v dd q0 nq0 nq1 v dd gnd q16 nq16 q17 nq17 v dd v dd_in vref npclk pclk sel_lvds gnd 8SLVS1118 nq10 q10 nq9 q9 nq8 q8 nq7 q7 nq6 q6 nq5 q5 3635 34 33 32 31 3028 2927 26 25 13 14 15 16 17 18 19 20 21 22 23 24 12 3 4 5 6 7 9 8 1011 12 48 47 46 45 44 43 42 41 40 39 38 37
3 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet 17 nq1 output differential output pair. lvpecl/ lvds interface levels. 18 q2 output differential output pair. lvpecl/ lvds interface levels. 19 nq2 output differential output pair. lvpecl/ lvds interface levels. 20 q3 output differential output pair. lvpecl/ lvds interface levels. 21 nq3 output differential output pair. lvpecl/ lvds interface levels. 22 q4 output differential output pair. lvpecl/ lvds interface levels. 23 nq4 output differential output pair. lvpecl/ lvds interface levels. 24 v dd power output power supply pin. 25 q5 output differential output pair. lvpecl/ lvds interface levels. 26 nq5 output differential output pair. lvpecl/ lvds interface levels. 27 q6 output differential output pair. lvpecl/ lvds interface levels. 28 nq6 output differential output pair. lvpecl/ lvds interface levels. 29 q7 output differential output pair. lvpecl/ lvds interface levels. 30 nq7 output differential output pair. lvpecl/ lvds interface levels. 31 q8 output differential output pair. lvpecl/ lvds interface levels. 32 nq8 output differential output pair. lvpecl/ lvds interface levels. 33 q9 output differential output pair. lvpecl/ lvds interface levels. 34 nq9 output differential output pair. lvpecl/ lvds interface levels. 35 q10 output differential output pair. lvpecl/ lvds interface levels. 36 nq10 output differential output pair. lvpecl/ lvds interface levels. 37 v dd power output power supply pin. 38 q11 output differential output pair. lvpecl/ lvds interface levels. 39 nq11 output differential output pair. lvpecl/ lvds interface levels. 40 q12 output differential output pair. lvpecl/ lvds interface levels. 41 nq12 output differential output pair. lvpecl/ lvds interface levels. 42 q13 output differential output pair. lvpecl/ lvds interface levels. 43 nq13 output differential output pair. lvpecl/ lvds interface levels. 44 q14 output differential output pair. lvpecl/ lvds interface levels. 45 nq14 output differential output pair. lvpecl/ lvds interface levels. 46 q15 output differential output pair. lvpecl/ lvds interface levels. 47 nq15 output differential output pair. lvpecl/ lvds interface levels. 48 v dd power output power supply pin. epad gnd_epad power exposed pad of package. connect to ground. [a] pull-up (pu) and pull-down (pd) resistors are indicated in parentheses. pull-up and pull-down refers to internal input resistors. for typical values, see dc input characteristics . t a ble 1 . pin de sc ript ions [a ] (cont .) number name type description
4 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet func t ion t a ble absolut e m a x im um ra t ings the absolute maximum ratings are stress ratings only. stresses greater than those listed below can cause permanent damage to th e device. functional operation of the 8SLVS1118 at absolute maximum ratings is not implied. exposur e to absolute maximum rating conditions may affect device reliability. t a ble 2 . sel_lv ds out put am plit ude se le c t ion t a ble sel_lvds qx output amplitude (mv) 0 (default) 750 (lvpecl) 1 450 (lvds) t a ble 3 . absolut e m a x im um ra t ings item rating supply voltage, v dd_in 3.6v inputs, v i -0.5v to 3.6v outputs, i o (lvds) continuous current surge current 10ma 15ma outputs, i o (lvpecl) continuous current surge current 50ma 100ma input sink/source, i ref 2ma maximum junction temperature, t j,max 125c storage temperature, t stg -65c to 150c esd C human body model [a] [a] according to jedec js-001-2012/jesd22-c101e. 2000v esd C charged device model [a] 1500v
5 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet dc ele c t ric a l cha ra c t e rist ic s t a ble 4 . dc i nput cha ra c t e rist ic s symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf r pulldown input pull-down resistor 51 k ? r pullup input pull-up resistor 51 k ? t a ble 5 . pow e r supply dc cha ra c t e rist ic s, v dd_i n ? v dd ? 3 .3 v 5 % , t a ? -4 0 c t o ? 8 5 c symbol parameter test conditions minimum typical maximum units v dd_in power supply voltage 3.135 3.3 3.465 v v dd output supply voltage 3.135 3.3 3.465 v i dd_in power supply current 15 ma i ee power supply current sel_lvds = 0 220 ma i dd output supply current sel_lvds = 1 480 ma t a ble 6 . pow e r supply dc cha ra c t e rist ic s, v dd_i n ? v dd ? 2 .5 v 5 % , t a ? -4 0 c t o ? 8 5 c symbol parameter test conditions minimum typical maximum units v dd_in power supply voltage 2.375 2.5 2.625 v v dd output supply voltage 2.375 2.5 2.625 v i dd_in power supply current 13 ma i ee power supply current sel_lvds = 0 215 ma i dd output supply current sel_lvds = 1 475 ma t a ble 7 . lv cm os i nput s dc cha ra c t e rist ic s, v dd_i n ? v dd ? 2 .5 v 5 % , 3 .3 v 5 % , t a ? -4 0 c t o ? 8 5 c symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd_in ? 3.3v 5% 2 v dd_in ? 0.3 v v dd_in ? 2.5v 5% 1.7 v dd_in ? 0.3 v v il input low voltage v dd_in ? 3.3v 5% -0.3 0.8 v v dd_in ? 2.5v 5% -0.3 0.7 v i ih input high current sel_lvds v dd_in ? v in ? v dd_max 150 a i il input low current sel_lvds v dd_in ? v dd_max, v in ? 0v -10 a
6 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet t a ble 8 . lv ds dc cha ra c t e rist ic s C v dd ?? 3 .3 v 5 % , t a ? -4 0 c t o ? 8 5 c symbol parameter test conditions minimum typical maximum units v od differential output voltage 370 490 mv ? v od v od magnitude change 50 mv v os offset voltage 1.9 2.7 v ? v os v os magnitude change 50 mv t a ble 9 . lv ds dc cha ra c t e rist ic s C v dd ? 2 .5 v 5 % , t a ? -4 0 c t o ? 8 5 c symbol parameter test conditions minimum typical maximum units v od differential output voltage 360 480 mv ? v od v od magnitude change 50 mv v os offset voltage 1.1 1.9 v ? v os v os magnitude change 50 mv t a ble 1 0 . lv pecl dc cha ra c t e rist ic s, v dd_i n ? v dd ? 2 .5 v 5 % , 3 .3 v 5 % , t a ? -4 0 c t o ? 8 5 c [a ] [a] core supply voltage cannot be lower than the output supply voltage. symbol parameter test conditions minimum typical maximum units i ih input high current pclk, npclk v in ? v dd_in ? v dd_max 150 a i il input low current pclk v in ? 0v, v dd_in ? v dd_max -10 a npclk v in ? 0v, v dd_in ? v dd_max -150 a vref reference voltage i ref = 100a, v dd_in ? 3.3v 2.05 2.45 v i ref = 100a, v dd_in ? 2.5v 1.55 1.85 v oh output high voltage [b] [b] outputs terminated with 50 ? to v dd C 2v. v dd C 1.1 v dd C 0.7 v v ol output low voltage [b] v dd C 1.8 v dd C 1.4 v
7 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet ac ele c t ric a l cha ra c t e rist ic s t a ble 1 1 . ac ele c t ric a l cha ra c t e rist ic s, v dd_i n ? v dd ? 2 .5 v 5 % , 3 .3 v 5 % , t a ? -4 0 c t o ? 8 5 c [a ] symbol parameter test conditions minimum typical maximum units f ref input frequency 2g h z ? v/ ? t input edge rate 1.5 v/ns t pd propagation delay [b], [c] pclk to any qx 290 400 ps t sk(o) output skew [d], [e] 40 60 ps t sk(p) pulse skew [f] f ref ? 100mhz 4 20 ps t sk(pp) part-to-part skew [e], [g] 200 ps t jit buffer additive phase jitter, rms; v ddin = v dd = 3.3v 750mv amplitude; see additive phase jitter f ref ? 156.25mhz; square wave, v pp ? 1v; integration range: 1khz C 40mhz 57 60 fs f ref ? 156.25mhz square wave, v pp ? 1v; integration range: 12khz C 20mhz 39 43 fs ? n ( ? 30m) clock single-side band phase noise ? 30mhz offset from carrier and noise floor -160 dbc/hz t r / t f output rise/ fall time 10C90% 160 300 ps 20C80% 105 200 ps v pp input voltage amplitude [h], [i] pclk, npclk 0.15 1.2 v v pp_diff differential input voltage amplitude pclk, npclk 0.3 2.4 v v cmr common mode input voltage [h], [i], [j] 1.125 v dd C ( v pp/2 ) v vo (pp) output voltage swing, peak-to-peak sel_lvds = 0 0.55 0.73 0.95 v sel_lvds = 1 0.30 0.43 0.60 v v diff_out differential output voltage swing, peak-to-peak sel_lvds = 0 1.10 1.46 1.90 v sel_lvds = 1 0.60 0.86 1.20 v v od differential output voltage lvpecl outputs sel_lvds ? 0, outputs loaded with 50 ? to v dd ? 2v 550 730 950 mv lvds outputs sel_lvds ? 1, outputs loaded with 100 ? 300 430 600 mv
8 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet v os offset voltage lvds outputs sel_lvds ? 1, v ddin = v dd = 3.3v 2.05 2.25 2.45 v sel_lvds ? 1, v ddin = v dd = 2.5v 1.25 1.45 1.65 v [a] electrical parameters are guaranteed over the specified ambient operating temperatur e range, which is established when the d evice is mounted in a test socket with maintained transverse airflow greater than 500lfpm. the device will meet specifications after thermal equ ilibrium has been reached under these conditions. [b] measured from the differential input crossing point to the differential output crossing p oint. [c] input v pp ? 400mv. [d] defined as skew between outputs at the same supply voltage and with equal load conditions. measur ed at the differential cros s points. [e] this parameter is defined in accordance with jedec standard 65. [f] output pulse skew is the absolute value of the difference of the propagation delay tim es: ? t plh C t phl ? . [g] defined as skew between outputs on different devices operating at the same supply voltage, same freque ncy, same temperature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cr oss points. [h] v il should not be less than -0.3v. vih should not be higher than v dd_in . [i] for single-ended lvcmos input applications, refer to application section, wiring the differential input to accept single-ended levels . [j] common mode input voltage is defined as the cross-point voltage. t a ble 1 1 . ac ele c t ric a l cha ra c t e rist ic s, v dd_i n ? v dd ? 2 .5 v 5 % , 3 .3 v 5 % , t a ? -4 0 c t o ? 8 5 c [a ] symbol parameter test conditions minimum typical maximum units
9 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet addit ive pha se j it t e r the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. ph ase nois e is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the po wer value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the funda mental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error ra te given a phase noise plot. figure 2 . addit ive pha se j it t e r. fre que nc y: 1 5 6 .2 5 m h z, i nt e gra t ion ra nge : 1 2 k h z t o 2 0 m h z ? 3 9 fs t ypic a l as with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipme nt. the noise floor of the equipment can be higher or lower than the noise floor of the dev ice. additive phase noise is dependent on bo th the noise floor of the input source and measurement equipment. measured using a wenzel 156.25mhz oscillator as the input source. ssb phase noise dbc/hz offset from carrier frequency (hz)
10 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet applic a t ions i nform a t ion re c om m e nda t ions for u nuse d i nput a nd out put pins i nput s pclk/npclk inputs for applications not requiring the use of the differential input, both pclk and npclk ca n be left floating. though not required , but for additional protection, a 1k ? resistor can be tied from pclk to ground. out put s lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvpecl outputs all unused lvpecl output pairs can be left floating. we recommend that there is no trace attached. both sides o f the differential output pair should either be left floating or terminated. vref the unused vref pin can be left floating. we recommend that there is no trace attached. wiring t he diffe re nt ia l i nput t o ac c e pt single -ende d le ve ls figure 3 shows how a differential input can be wired to accept single ended levels. the reference vol tage v 1 ? v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bi as circuit should be lo cated as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 1.8v and v dd ? 1.8v, r1 and r2 value should be adjusted to set v 1 at 0.9v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termin ation at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 a nd r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. figure 3 . re c om m e nde d sc he m a t ic for wiring a diffe re nt ia l i nput t o ac c e pt single -e nde d le ve ls
11 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differen tial input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster th an 1v/ns. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-en ded applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd ? 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purpo ses. the datasheet specifications are characterized and guaranteed by using a differential signal. 2 .5 v lv pecl i nput w it h built -in 5 0 ? t e rm ina t ion i nt e rfa c e the pclk /npclk with built-in 50 ? terminations accept lvds, lvpecl, lvcmos and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 4 to figure 5 show interface examples for pclk /npclk with built-in 50 ? termination input driven by the most common driver types. the input interfaces suggested here are exa mples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the d river component to confirm the dri ver termination requirements. figure 4 . pclk / npclk i nput w it h built -in 5 0 ? drive n by a n lv ds drive r figure 5 . pclk / npclk i nput w it h built -in 5 0 ? drive n by a n lv pecl drive r pclknpclk vt receiv er withbuilt-in 50 lvds 3 .3v or 2.5v 2.5v zo = 50 zo = 50 pclknpclk vt receiv er withbuilt-in 50 r118 lvpecl 2.5v 2.5v zo = 50 zo = 50
12 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet 3 .3 v lv pecl i nput w it h built -in 5 0 ? t e rm ina t ion i nt e rfa c e the pclk /npclk with built-in 50 ? terminations accept lvds, lvpecl, lvcmos and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 6 to figure 7 show interface examples for pclk /npclk with built-in 50 ? termination input driven by the most common driver types. the input interfaces suggested here are exa mples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the d river component to confirm the dri ver termination requirements. figure 6 . pclk / npclk i nput w it h built -in 5 0 ? drive n by a n lv ds drive r figure 7 . pclk / npclk i nput w it h built -in 5 0 ? drive n by a n lv pecl drive r pclknpclk vt receiverwith built-in 50 lvds 3.3v or 2.5v 2.5v zo = 50 zo = 50 pclknpclk vt receiv er withbuilt-in 50 r118 lvpecl 2.5v 3.3v zo = 50 zo = 50
13 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet lv ds drive r t e rm ina t ion for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a ful l lin e of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 8 can be used with either type of output structure. figure 9 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capac itor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output s tructure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input recei vers amplitude and common-mode input range should be verified for compatibility with the output. figure 8 . st a nda rd lv ds t e rm ina t ion figure 9 . opt iona l lv ds t e rm ina t ion
14 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet t e rm ina t ion for 3 .3 v lv pecl out put s the clock layout topology shown below is a typical termination for lvpecl outputs. the two differe nt layouts mentioned are recommended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) o r current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distor tion. figure 10 and figure 11 show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it woul d be recommended that the b oard designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 1 0 . 3 .3 v lv pecl out put t e rm ina t ion figure 1 1 . 3 .3 v lv pecl out put t e rm ina t ion r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v +_
15 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet t e rm ina t ion for 2 .5 v lv pecl out put s figure 12 and figure 13 show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v dd C 2v. for v dd ? 2.5v, the v dd C 2v is very close to ground level. the r3 in figure 13 can be eliminated and the termination is shown in figure 14 . figure 1 2 . 2 .5 v lv pecl drive r t e rm ina t ion ex a m ple figure 1 3 . 2 .5 v lv pecl drive r t e rm ina t ion ex a m ple figure 1 4 . 2 .5 v lv pecl drive r t e rm ina t ion ex a m ple 2.5v lvpecl driver v dd = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + C 2.5v lvpecl driver v dd = 2.5v 2.5v 50 50 r150 r250 r318 + C 2.5v lvpecl driver v dd = 2.5v 2.5v 50 50 r150 r250 + C
16 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet v fqfn epad t he rm a l re le a se pa t h in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorpora ted on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 15 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearan ce should be desi gned on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to a void any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pa ttern must be connected to ground through these vias. the vias act as heat pipes. the number of vias (i.e. he at pipes) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, the rmal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possibl e. it is also recommended that the via diameter should be 12mils to 13mils (0.30mm to 0.33 mm) with 1oz copper via barrel plating. this i s desirable to avoid any solder wicking inside the via during the soldering process which may result in vo ids in solder between t he exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the ex posed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note o n the surface mount assembly of amkor?s thermally/ electrically enhance lead-frame base package, amkor technology. figure 1 5 . p.c. asse m bly for ex pose d pa d t he rm a l r e le a se pa t h C side v ie w (dra w ing not t o sc a le ) solder solder pin pin eposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
17 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet ca se t e m pe ra t ure conside ra t ions this device supports applications in a natural convection environment which does not have any therma l conductivity through ambient air. the printed circuit board (pcb) is typically in a sealed enclosure without any natural or forced air flow and is kept at or bel ow a specific temperature. the device package design incorporates an exposed pad (epad) with enhanced thermal paramete rs which is soldered to the pcb where most of the heat escapes from the bottom exposed pad. for this type of application, it is recommended to use the junction-to-board thermal characterization parameter ? jb (psi-jb) to calculate the junction temperature (t j ) and ensure it does not exceed the maximum allowed junction temperature in the absolute maximum ratings table. the junction-to-board thermal characterization parameter, ? jb, is calculated using the following equation: t j ? t cb ? ? jb ? p d, where t j ? junction temperature at steady state condition in ( o c). t cb ? case temperature (bottom) at steady state condition in ( o c). ? jb ? thermal characterization parameter to report the difference between junction temperature and the temperature of th e board measured at the top surface of the board. p d ? power dissipation (w) in desired operating configuration. the epad provides a low thermal resistance path for heat transfer to the pcb and represents the key pathway to transfer heat away from the ic to the pcb. its critical that the connection of the exposed pad to the pcb is properl y constructed to maintain the desi red ic case temperature (t cb ). a good connection ensures that temperature at the exposed pad (t cb ) and the board temperature (t b ) are relatively the same. an improper connection can lead to increased junction temperature, increased power consumption and decre ased electric al performance. in addition, there could be long-term reliability issues and increased failure rate. example calculation for junction temperature (t j ): t j ? t cb ? ? jb ? p d for the above variables, the junction temperature is equal to 107.1 o c. since this is below the maximum junction temperature of 125 o c, there are no long-term reliability concerns. package type 48-vfqfn body size (mm) 7 ? 7 ? 0.8 epad size (mm) 5.65 ? 5.65 thermal via 5 ? 5 matrix ? jb 1.2 o c/w t cb 105 o c p d 1.715w t j t cb
18 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet pow e r conside ra t ions (lv ds out put m ode ) this section provides information on power dissipation and junction temperature for the 8SLVS1118. equations and example calculations are also provided. 1. power dissipation. the following is the power dissipation for v dd_in = v dd = 3.465v, which gives worst case results. maximum current at 85c: i dd_in_max + i dd_max = 495ma. power_ max = 3.465v x 495ma = 1715mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 22.4c/w per table 12 . therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.715w * 22.4c/w = 123.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, su pply voltage, air flow and the type of board (multi-layer). t a ble 1 2 . t he rm a l re sist a nc e ? j a for 4 8 -v fqfn , forc e d conve c t ion ? ja (c/w) vs. air flow (m/s) meters per second 0 1 2 48-lead vfqfn multi-layer pcb, jedec standard test boards 22.4 18.9 17.4
19 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet pow e r conside ra t ions (lv pecl out put m ode ) this section provides information on power dissipation and junction temperature for the 8SLVS1118. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8SLVS1118 is the sum of the core power plus the power dissipated at the out put(s). the following is the power dissipation for v dd_in = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated at the outputs. power (core) max = v dd_in * i ee_max = 3.465v * 220ma = 762.3mw power (outputs) max = 35mw/loaded output pair if all outputs are loaded, the total power is 18 * 35mw = 630mw total power_ max (3.465v, with all outputs switching) = 762.3mw + 630mw = 1392.3mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 22.4c/w per table 13 . therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.3923w * 22.4c/w = 116.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, su pply voltage, air flow and the type of board (multi-layer). t a ble 1 3 . t he rm a l re sist a nc e ? j a for 4 8 -v fqfn , forc e d conve c t ion ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 22.4c/w 18.9c/w 17.4c/w
20 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. lvpecl output driv er circuit and termination are shown in table 10 . figure 1 6 . lv pecl drive r circ uit a nd t e rm ina t ion to calculate worst case power dissipation at the output(s), use the following equations which assume a 50 ? load, and a termination voltage of v dd C 2v. ? for logic high, v out = v oh_max = v dd_max C 0.7v (v dd_max C v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v dd_max C 1.4v (v dd_max C v ol_max ) = 1.4v pd_h is the power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max C (v dd_max C 2v))/r l ] * (v dd_max C v oh_max ) = [(2v C (v dd_max C v oh_max ))/r l ] * (v dd_max C v oh_max ) = [(2v C 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max C (v dd_max C 2v))/r l ] * (v dd_max C v ol_max ) = [(2v C (v dd_max C v ol_max ))/r l ] * (v dd_max C v ol_max ) = [(2v C 1.4v)/50 ? ] * 1.4v = 16.8mw total power dissipation per output pair = pd_h + pd_l = 35mw v out v dd v dd - 2v q1 rl
21 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet pa c k a ge out line dra w ings figure 1 7 . pa c k a ge out line dra w ings C she e t 1
22 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet figure 1 8 . pa c k a ge out line dra w ings C she e t 2
23 ?2017 integrated device technology, inc. july 17, 2017 8SLVS1118 datasheet m a rk ing dia gra m orde ring i nform a t ion t a ble 1 4 . orde ring i nform a t ion part/order number marking package shipping packaging temperature 8SLVS1118nlgi idt8SLVS1118nlgi 48-lead vfqfn, lead-free tray -40c to +85c 8SLVS1118nlgi8 idt8SLVS1118nlgi 48-lead vfqfn, lead-free; quadrant 1 (eia-481-c) tape & reel, pin 1 orientation: eia-481-c 8SLVS1118nlgi/w idt8SLVS1118nlgi 48-lead vfqfn, lead-free; quadrant 2 (eia-481-d/e) tape & reel, pin 1 orientation: eia-481-d/e t a ble 1 5 . pin 1 orie nt a t ion in t a pe a nd re e l pa c k a ging part number suffix pin 1 orientation illustration 8SLVS1118nlgi8 quadrant 1 (eia-481-c) 8SLVS1118nlgi/w quadrant 2 (eia-481-d/e) 1. line 1, line 2, and line 3 indicates the part number. 2. line 4: ? # indicates stepping. ? yyww indicates the date code (yy denotes the last two digits of the year, and ww denotes a work week number that the part was assembled. ? $ indicates the mark code.
8SLVS1118 datasheet 24 ?2017 integrated device technology, inc. july 17, 2017 disclaimer integrated device te chnology, inc. (idt) and its aff iliated companies (herein referred to as idt) reserve the right to modify the products and/or specific ations described herein at any time, without notice, at idts sole discretion. performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of idt's products for any particular purpose, an implied warran ty of merchantability, or non-infringement of the intellectual p roperty rights of others. this documen t is presented only as a guide and does not convey any license under intellectual propert y rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other c ountries. other trademarks used herein are the property of idt or their respective third party owners. for datas heet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. t e c h support www.idt.com/go/support sa le s 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corpora t e h e a dqua rt e rs 6024 silver creek valley road san jose, ca 95138 usa www.idt.com re vision h ist ory revision date description of change july 17, 2017 initial release.

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